Scanning for transmitting stations on channel when using a two-way radio transceiver is commonly known in the art. With the advent of receivers incorporating Digital Signal Processors (DSP), many different algorithms have been developed to effectively detect radio frequency (RF) energy on a channel for alerting a user to the activity. Each algorithm provides a particular method in scanning for such activity. For example, a standard or conventional scanning technique moves from channel to channel in some predetermined sequence to detect channel activity. In contrast, a priority scan allows the user to remain on one channel while the radio transceiver periodically checks one or more other channels designated as “priority” channels for activity. When activity is detected on a priority channel, the receiver will move to that channel in view of its “priority” designation. Carrier Sense Multiple Access (CSMA) protocols also depend on fast channel acquisition as part of the ALOHA strategy to detect and correct “collisions” created when two client transmitters both attempted to send a transmission packet at the same time. Those skilled in the art will recognize that Aloha, also called the Aloha method refers to a simple communications scheme in which each transmitter in a network sends data whenever there is a frame to send. If the frame successfully reaches the receiver, the next frame is sent. If the frame fails to be received at the destination, it is sent again. This protocol was originally developed at the University of Hawaii for use with satellite communication systems in the Pacific region
To maximize the effectiveness of any scan strategy or channel acquisition protocol it is of paramount importance to determine if an RF modulated signal having correct signaling occupies the targeted channel as quickly as possible. An efficient channel acquisition should be accomplished while minimizing digital processing, current drain, and latency. Fast scan or channel acquisition capability reduces the time required to check a targeted RF channel, which correspondingly translates into reduced time to scan a complete scan list, reduced audio interruption caused when checking the priority channel, or a reduction in the opportunity of acquisition “misses” when executing an ALOHA channel acquisition. The first step in the execution of a scan sequence is to determine if there is any RF carrier of any type occupying the targeted RF channel. Given that in most cases a RF channel that is being checked will not have a signal of any type present, an initial channel activity check, or RF carrier detect, can mitigate the need for further processing, such as filtering and demodulation of channel noise, before continuing with the scan sequence. Most legacy scan sequences require digital processing of the receive channel necessitating a period when the receiver is listening for activity on an active channel and then moves to scan the next channel for potential channel activity. For digitally based scan sequences, it can require from 7 mS to 10 mS to determine the presence of RF signal once the RF carrier is present at the input of the receiver antenna. Therefore, the period needed for the receiver to move to the priority channel from an active channel, check for channel activity on the priority channel, and move back to the active channel if no activity is detected on the priority channel, necessitates up to 15 mS of “round trip time”. This creates a gap or “hole” in the audio stream even though the receiver is switched back to the active channel very quickly. Typically for an audio hole to be undetectable by a user's ear, the hole must be approximately 5 milliseconds (mS) or less in duration.
A typical receiver topology utilizing a scanning function is illustrated in the prior art block diagram of FIG. 1. The receiver 100 includes a first filter 101 which receives an RF signal and supplies the signal to a low noise amplifier (LNA) 103. The LNA is a Variable Gain Amplifier (VGA) to support automatic gain control (AGC) functionality in order to prevent the RF energy at the front-end of the receiver from exceeding a predetermined range. The VGA gain is set by the AGC during closed loop operation by varying the output voltage of the digital-to-analog converter (DAC) 119 which is within a AGC controller 113. The amplified signal from LNA 103 is supplied to second filter 105 and a mixer 107. The down-mixed signal is then conveyed to filter 109 and subsequently converted to a digital signal by sampling the analog signal at the input of analog-to-digital converter (ADC) 111. The digital signal at the output of the ADC may then be post-processed by an application specific integrated circuit (ASIC) for decimation, filtering and formatting circuit 123, a digital signal processor (DSP) 125 and a host such as a microprocessor 127 for providing control functions.
The function of the AGC controller 113 is determined by the AGC logic 121 which translates information from the signal magnitude estimator to determine the output voltage of the AGC DAC 119. In operation, the signal magnitude estimator 115 receives information indicative of the received signal strength from the ADC 111 and conveys said information to a plurality of comparators 117, with each comparator having a specific threshold from a plurality of thresholds as set by AGC logic 121. The thresholds are supplied digitally with 8 bit resolution to the AGC logic 121 for the controlling operation of the LNA 103. The processing speed of AGC logic controller 121 and host 127 are may be proportional to a common clock source 129. The AGC logic, ADC, and ASIC processing characteristic are all programmable by the host though a serial port interface (SPI) port 131.
It should be evident to those skilled in the art that the receiver 100 is designed for autonomous AGC operation using the host 127 that is able to control the AGC thresholds 117 via SPI programming. The plurality of thresholds for the plurality of comparators 117 allows the AGC controller 113 to respond differently depending of the level of the RF present at ADC 111. Typically, these prior art AGC systems operate only to protect the receiver against very strong signal conditions at the receiver input where typically, only the last 8 most significant bits (MSBs) from a 16 bit ADC 111 are necessary to determine a range of attenuation for the LNA 103. The DSP 125 and host 127 continuously process the sampled data from ADC 111 for creating a signal in the digital domain by DSP processing. When used in connection with a scanning algorithm, the AGC acts only to control RF signal levels at the front end of the receiver and does nothing to mitigate audio holes generated when the receiver is scanning for active channel.
FIG. 2 illustrates one specific type of implementation of the AGC control circuit like that shown in FIG. 1. The AGC control system 200 utilizes an analog input to a sigma-delta ADC 201 which in turn supplies a digital bit stream to a signal magnitude estimator 203. The signal magnitude estimator 203 includes a cascaded integrator comb (CIC) filter 205 which supplies a filtered input to a sum of squares (SOS) estimator 207. As will be evident to those skilled in the art, a sum of squares estimator utilizes the sum of the squares of the difference of a dependent variable and its grand mean to calculate an estimated value. This value is supplied to a plurality of comparators 209 that work with a series of programmable thresholds to provide a logarithmic output to AGC control logic 211.
Accordingly, the AGC control system 200 uses this logarithmic value along with a programmable clock divider 213 to provide an input to an AGC DAC 215. The output of the AGC DAC is then used to control the gain of an LNA like that shown in prior art FIG. 1. In operation, the AGC system 200 uses an architecture where a digital signal is created from an analog signal using the sigma delta ADC 201 where the signal magnitude estimator 203 determines an estimate of the digital signal's magnitude. This magnitude estimate is then fed to k comparators 209 which compare the signal magnitude to k programmable thresholds. Making k comparisons, the signal magnitude is determined to be within one of k+1 regions. This result is passed to the AGC control logic 211 which then determines if the AGC gain should be adjusted. The rate at which the gain is increased or decreased is set by slew rates determined by the programmable clock dividers 213. The resulting AGC gain value is set by adjusting the output voltage of the AGC DAC 215 which drives the adjustable gain of the system. A closed loop AGC system is therefore realized in that the level of the received signal at the input of the ADC 201 is determined by the gain of the receiver LNA, wherein the gain of the receiver LNA is set by the AGC DAC 215 as determined by the AGC control logic 211, wherein the AGC logic response is dictated by signal magnitude estimator 209 which estimates the signal level at the input of the ADC 201.
One of the limitations associated in using this type of topology for scan or channel acquisition is the processing latency associated with the ASIC and DSP to achieve carrier detect. Although this prior art topology provides for a very robust AGC control system for the LNA, it does nothing to mitigate the disruption in the audio when this topology is used in a priority scan mode, neither is it maximally efficient for carrier detect determination in CSMA or legacy scan sequences. In priority scan applications, the legacy receiver topologies and channel acquisition strategies elongate the “audio hole” created when checking the priority channel for a RF carrier, which negatively effects the radio operator's perception of the audio quality of the received signal. In addition, multiple retries in a CSMA system reduces system capacity thereby degrading overall capability. Consequently, the need exists to provide an optimum solution to reduce both the audio hole generated during prior scan and improve channel acquisition efficiency while using a strategy that is easily adaptable to existing receive topologies